Title :
Modelling the behavior of solder joints for wafer level SiP
Author :
Strusevich, N. ; Stoyanov, S. ; Liu, D. ; Bailey, C. ; Richardson, A. ; Dumas, N. ; Yannou, J.M. ; Georgel, V.
Author_Institution :
Centre for Numerical Modelling & Process Anal., Greenwich Univ., London
Abstract :
Design for manufacture of system-in-package (SiP) structures is dependent on a number of physical processes that affect the final quality of the package in terms of its performance and reliability. Solder joints are key structures in a SiP and their behavior can be the critical factor in terms of reliability. This paper discusses the results from a research programme on design for manufacturing of system in package (SiP) technologies. The focus of the paper is on thermo-mechanical modelling of solder joints. This includes the behavior of the joints during testing plus some important insights into the reflow process and how physical phenomena taking place at the assembly stage can affect solder joint behavior. Finite element analysis of a numerical model of an SiP structure with various design parameters is discussed. The goal of this analysis is to identify the most promising combination of design parameters which guarantee longer lifetime of the solder joints and hence the SiP component. The parameters that were studied are the size of the package (i.e. number of solder joints per row), the presence of the underfill and/or the reinforcement as well as the thickness of the passive die. Discussion was also provided on phenomena that take place during the reflow process where the solder joints are formed. In particular, the formation of intermetallics at the solder-pad interfaces
Keywords :
alloys; design for manufacture; integrated circuit metallisation; integrated circuit modelling; reflow soldering; reliability; system-in-package; wafer level packaging; design for manufacture; finite element analysis; intermetallic formation; passive die thickness; reflow process; solder joints; solder-pad interface; system-in-package; thermo-mechanical modelling; wafer level SiP; Assembly; Finite element methods; Manufacturing processes; Packaging; Pulp manufacturing; Semiconductor device modeling; Soldering; Testing; Thermomechanical processes; Wafer scale integration;
Conference_Titel :
Electronics Packaging Technology Conference, 2006. EPTC '06. 8th
Conference_Location :
Singapore
Print_ISBN :
1-4244-0664-1
Electronic_ISBN :
1-4244-0665-X
DOI :
10.1109/EPTC.2006.342703