A 20GS/s low-power BiCMOS comparator using an active inductor load

A 20GS/s BiCMOS latched comparator for highspeed, low-power Analog-to-Digital Converter (ADC) is proposed. The resister load of conventional current-steering comparator is replaced by an active inductor load made by a MOS transistor and a resister. This solution extends the bandwidth of the circuit without excessive power dissipation. Implemented in 0.35μm SiGe BiCMOS technology, this comparator only occupies a die area of 97×67 μm2 with a power dissipation of 31 mW from a 3.3-V power supply. Operating with an input frequency of 2 GHz, the circuit can oversample up to 20 GS/s with 4 bits of resolution; while operating at Nyquist, the comparator can sample up to 20 GS/s with 3 bits resolution. This design achieves a considerable trade-off between power, speed and resolution.