Transistor width dependence of LER degradation to CMOS device characteristics

When transistor gate length is scaled down, the impact of transistor poly gate line edge roughness (LER) on device characteristics becomes significant. In this work, we study the dependence on transistor width of the low spatial frequency LER induced CMOS device Ion/Ioff degradations, based on TCAD simulation results and silicon data. Methodology to account for LER effects in device optimization is also discussed. We found that when the transistor width becomes comparable to the LER spatial period, the resulting transistor Ion/Ioff degradation presents a very different signature from that of wide transistor cases. We found that for narrow width transistors, the scatter clouds on the Ion/Ioff plot stretch out along the Ion/Ioff curve direction and compress vertically toward the ideal Ion/Ioff curve resulting in transistor parametric yield loss.