Structural design for Cu/low-K larger die flip chip package

The low-k materials have intrinsically lower modulus and poorer adhesion compared to the commonly used dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of a Cu/low-k larger die flip chip package. Furthermore, underfill selection for a Cu/low-k larger die package is also a challenging issue. In this paper, a two-dimensional finite element analysis was performed on the diagonal cross-section of the package with emphasis on thermally induced stress in low-k layer, inelastic strain in solder bumps and package warpage. A large die flip chip package with 20 times20 mm die size, 150 micron bump pitch on a 45 times 45 mm buildup organic substrate has been undertaken for analysis. A series of parametric study is performed by varying different crucial package dimensions which play an important role in reducing the stress in low-k layer and improve solder fatigue life. Modeling was also performed to select the suitable mechanical properties of underfill, core and buildup layer which can minimize stress in low-k structure and minimize strain in the solder bumps.