Thermal induced warpage characterization for printed circuit boards with shadow moire system

Thermal induced warpage of printed circuit boards during high temperature reflow of assembly process can cause significant production and reliability problems. Fine solder pad pitch, high component density, and low thickness profile are commonly adopted in advanced printed circuit board development nowadays. Moreover, lead-free solder joint requires higher reflow temperature which generates more severe warpage. As such, accurate predicting printed circuit board warpage becomes more and more critical for printed circuit board design and process optimum in order to improve product reliability and process yield. However, most of warpage measurements have some difficulties and limitations, especially in temperature variance procedure. Hence, the warpage prediction method can be hardly verified with the actual measurement results. In the present study, printed circuit board warpage was evaluated with a non-contact realtime shadow moire technique. A high temperature oven was also integrated into the system in order to simulate the solder reflow process. Furthermore, finite element analyses were conducted to simulate the printed circuit board warpage under different temperatures. The measurement results were used to further validate and improve finite element models. It was found that the results simulated with the simplified finite element model had great error with the experimental results. Hence, an advanced finite element model was established by directly importing the printed circuit board design to inherit the intrinsic properties of the board layout. The results were matched well with the experimental results. Consequently, this valuable finite element model could be utilized to identify design problems in printed circuit board layout and assembly processes during the design stage which might result in cost reduction and product reliability improvement