Title :
RF-MEMS wafer-level packaging using through-wafer via technology
Author :
Tian, J. ; Iannacci, J. ; Sosin, S. ; Gaddi, R. ; Bartek, M.
Author_Institution :
Lab. of High-Frequency Technol. & Components/DIMES, Delft Univ. of Technol.
Abstract :
This paper presents wafer-level packaging (WLP) solution for RF-MEMS applications based on through-wafer via (TWV) technology in high-resistivity silicon (HRS). A pre-processed HRS capping wafer containing recesses and vertical Cu-plated TWV interconnect is, after alignment, bonded to the RF-MEMS wafer providing environmental protection and easy signal access. Optionally, cavities can be formed simultaneously with TWV in the capping wafer, which allows hybrid co-integration of additional IC dies while maintaining overall thickness of the resulting SMT compatible package. This cavity can also be used for a first-level wafer-to-wafer alignment accuracy check. After bonding, the s-parameter measurement at giga hertz level shows little influence introduced by the capping substrate.
Keywords :
S-parameters; integrated circuit interconnections; micromechanical devices; surface mount technology; wafer level packaging; RF-MEMS wafer-level packaging; SMT compatible package; capping wafer; high-resistivity silicon; hybrid co-integration; integrated circuit dies; s-parameter measurement; through-wafer via technology; vertical Cu-plated TWV interconnect; wafer-to-wafer alignment; Costs; Etching; Integrated circuit interconnections; Micromechanical devices; Packaging; Protection; Radiofrequency microelectromechanical systems; Surface-mount technology; Wafer bonding; Wafer scale integration;
Conference_Titel :
Electronics Packaging Technology Conference, 2006. EPTC '06. 8th
Conference_Location :
Singapore
Print_ISBN :
1-4244-0664-1
Electronic_ISBN :
1-4244-0665-X
DOI :
10.1109/EPTC.2006.342755