Title :
On shrinking wide compressors
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
fDate :
30 Apr-3 May 1995
Abstract :
Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISRs) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISRs that may include several hundred stages. Wide MISRs pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of shrinking a MISR so that it samples multiple signals at every stage. The ultimate shrinkage occurs when only the parity of the sampled signals is compressed. This is the case when a MISR is replaced by a single-input signature register (SISR). Issues like detection probability loss, test length penalty, fault coverage degradation, are some of the disadvantages that may arise from the MISR shrinkage. Minimizing the effect of these issues is a precondition to the success of this method
Keywords :
built-in self test; fault diagnosis; integrated circuit testing; logic testing; shift registers; MISRs; built-in self-test; detection probability loss; fault coverage degradation; multiple-input signature registers; parity; pseudo-random test; test length penalty; wiring overhead; Built-in self-test; Circuit faults; Circuit testing; Compressors; Degradation; Fault detection; Hardware; Jacobian matrices; Packaging; Registers;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512625
