Signature analysis and aliasing for sequential circuits

Many built-in self-test techniques insert test registers and thus segment the circuit into subcircuits which are surrounded by test registers. If not all registers of the circuit are enhanced to test registers, the resulting subcircuits are sequential. Errors in their test responses generally depend on the state of the subcircuit and hence can be correlated both in space and in time. In this paper results on the probability of aliasing that up to now have been proved only for combinational circuits are generalized. It is shown that for almost all faults of the considered sequential circuits the aliasing probability asymptotically approaches 2^-k or is 0 if a signature analyzer with an irreducible characteristic polynomial is used and certain test lengths are avoided. This limiting value can be used as a good approximation of the actual aliasing probability at practical test lengths