Model of n-type polycrystalline silicon thin film transistors under DC bias stress

The density of trap states distribution in the bulk of polycrystalline silicon thin film transistor is modeled by constant deep states and exponential tail states. Pao-Sah method is used to model the hot carrier degradation behavior. At low gate voltage bias stress, tail states increase with the stress time, which indicates the generation of local strain bonds near the drain. At higher gate voltage bias states, both deep states and tail states increase with the stress time, which indicates the generation of both dangling bonds and local strain bonds near the drain. Transfer characteristic degradation with stress time is calculated. The results are agreed with the available experiment data successfully.