Title :
Resynthesis for sequential circuits designed with a specified initial state
Author :
Yotsuyanagi, Hiroyuki ; Kajihara, Seiji ; Kinoshita, Kozo
Author_Institution :
Dept. of Appl. Phys., Osaka Univ., Japan
fDate :
30 Apr-3 May 1995
Abstract :
This paper presents a retiming and redundancy removal method for a sequential circuit with a specified initial state so that the resynthesized circuit has a state corresponding to the initial state and gives same behavior for any input sequences of the original circuit. Experimental results show the proposed method can optimize circuits as well as the method which does not consider the specified initial state
Keywords :
circuit optimisation; flip-flops; logic CAD; redundancy; sequential circuits; timing; flip-flops; input sequences; logic optimisation; redundancy removal method; resynthesized circuit; retiming method; specified initial state; synchronous sequential circuits; Circuit testing; Combinational circuits; Flip-flops; Logic circuits; Logic gates; Logic testing; Optimization methods; Physics; Redundancy; Sequential circuits;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512630
