Testability metrics for synthesis of self-testable designs and effective test plans

Author

Vahidi, Mahsa ; Orailoglu, Alex

Author_Institution

Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA

fYear

1995

fDate

30 Apr-3 May 1995

Firstpage

170

Lastpage

175

Abstract

We propose a set of unified metrics for self-testability which are portable across different phases of synthesis. Furthermore, applicability of the proposed test metrics is verified through extensive experiments on benchmark designs

Keywords

VLSI; built-in self test; design for testability; high level synthesis; integrated circuit design; logic CAD; BIST; DFT; VLSI; benchmark designs; effective test plans; high level synthesis; self-testable designs; synthesis phases; testability metrics; unified metrics; Area measurement; Automatic testing; Benchmark testing; Built-in self-test; Circuit testing; Computer science; High level synthesis; System testing; Time measurement; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1995. Proceedings., 13th IEEE

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7000-2

Type

conf

DOI

10.1109/VTEST.1995.512633

Filename

512633

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2278949