Title :
High level fault modeling of asynchronous circuits
Author :
Lu, Ding ; Tong, Carol Q.
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
fDate :
30 Apr-3 May 1995
Abstract :
A method is proposed for high level fault modeling of asynchronous circuits which are described by the signal transition graph. Transitional fault models are introduced. It is shown that the transitional faults are the direct mappings of most of the low level faults
Keywords :
asynchronous circuits; fault diagnosis; logic testing; signal flow graphs; timing; asynchronous circuits; high level fault modeling; self-timed circuits; signal transition graph; stuck-at-false model; stuck-at-true model; transitional fault models; Asynchronous circuits; Automatic testing; Circuit faults; Circuit testing; Clocks; Combinational circuits; Integrated circuit interconnections; Latches; Logic; Sequential analysis;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512636
