• DocumentCode
    2279000
  • Title

    High level fault modeling of asynchronous circuits

  • Author

    Lu, Ding ; Tong, Carol Q.

  • Author_Institution
    Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
  • fYear
    1995
  • fDate
    30 Apr-3 May 1995
  • Firstpage
    190
  • Lastpage
    195
  • Abstract
    A method is proposed for high level fault modeling of asynchronous circuits which are described by the signal transition graph. Transitional fault models are introduced. It is shown that the transitional faults are the direct mappings of most of the low level faults
  • Keywords
    asynchronous circuits; fault diagnosis; logic testing; signal flow graphs; timing; asynchronous circuits; high level fault modeling; self-timed circuits; signal transition graph; stuck-at-false model; stuck-at-true model; transitional fault models; Asynchronous circuits; Automatic testing; Circuit faults; Circuit testing; Clocks; Combinational circuits; Integrated circuit interconnections; Latches; Logic; Sequential analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 1995. Proceedings., 13th IEEE
  • Conference_Location
    Princeton, NJ
  • ISSN
    1093-0167
  • Print_ISBN
    0-8186-7000-2
  • Type

    conf

  • DOI
    10.1109/VTEST.1995.512636
  • Filename
    512636
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2279000