Title :
Checking experiments to test latches
Author :
Makar, Samy R. ; McCluskey, E.J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
fDate :
30 Apr-3 May 1995
Abstract :
Necessary and sufficient conditions for exhaustive functional tests (checking experiments) of 2-state latches are derived. These conditions are used to derive minimum-length checking experiments. The checking experiment for the D-latch is simulated using an HSpice implementation of the transmission gate latch. All detectable shorted interconnects, open interconnects, short-to-power, short-to-ground, stuck-open, and stuck-on faults are detected. A pin fault test set and a multiplexer-based test set are also simulated. These tests miss some faults detected by the checking experiment
Keywords :
CMOS logic circuits; SPICE; circuit analysis computing; fault diagnosis; finite state machines; integrated circuit testing; logic testing; sequential circuits; 2-state latches; 2-state state machines; CMOS; D-latch; HSpice implementation; checking experiments; detectable shorted interconnects; exhaustive functional tests; minimum-length checking; multiplexer-based test set; open interconnects; pin fault test set; sequential elements; short-to-ground faults; short-to-power faults; simulation; stuck open faults; stuck-on faults; transmission gate latch; Circuit faults; Clocks; Computational modeling; Fault detection; Integrated circuit interconnections; Latches; Logic; Sufficient conditions; Testing; Voltage;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512637
