Fault coverage analysis of RAM test algorithms

Author

Riedel, Marc ; Rajski, Janusz

Author_Institution

MACS Lab., McGill Univ., Montreal, Que., Canada

fYear

1995

fDate

30 Apr-3 May 1995

Firstpage

227

Lastpage

234

Abstract

A methodology for evaluating the fault coverage of RAM test algorithms is proposed and the architecture of a flexible software analysis program is described. The analysis, performed for arbitrary test sequences, provides a comprehensive set of coverage statistics for functional cell-array faults. An overview of the analysis capabilities of the program is given, the fault state transition conditions for several representative fault classes are specified, and coverage analyses results for a variety of test algorithms are presented

Keywords

fault diagnosis; integrated circuit testing; integrated memory circuits; random-access storage; RAM test algorithms; arbitrary test sequences; coverage statistics; fault coverage; fault state transition conditions; flexible software analysis program; functional cell-array faults; representative fault classes; semiconductor memories; test algorithms; Algorithm design and analysis; Automatic testing; Circuit faults; Laboratories; Performance analysis; Random access memory; Read-write memory; Semiconductor device testing; Software testing; Statistical analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1995. Proceedings., 13th IEEE

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7000-2

Type

conf

DOI

10.1109/VTEST.1995.512642

Filename

512642