Modeling and analysis of the dead-time effects in parallel two-level voltage source inverters

A necessary blanking-time used to prevent a short circuit in the inverter phase leg, finite turn-on and turnoff times of switching devices, and forward voltage drops of switching devices and anti-parallel diodes are known to cause load dependent distortion to inverter output voltages. The objective of this paper is to gain the understanding how the overall effects of the above-mentioned factors affect the circulating current generation between the parallel-connected two-level voltage source inverters. To meet this objective, a circulating current model taking these effects into account is developed. The model, which is an average model in nature, gives an analytical way to consider the significance of these effects to the circulating current generation. To verify the validity of the developed model, the circuit simulation results are shown and compared with the analytical results. The illustrations show that the results obtained with the developed model are in good agreement with the circuit simulations.