Title :
Diagnosis of scan path failures
Author :
Edirisooriya, Samantha ; Edirisooriya, Geetani
Author_Institution :
Motorola Comput. Group, USA
fDate :
30 Apr-3 May 1995
Abstract :
Scan based diagnostic schemes are used to diagnose faults in faulty circuits. Such techniques assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain may occupy nearly 30% of a chip area and hence warrants consideration during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains
Keywords :
combinational circuits; design for testability; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; faulty circuits; logic circuitry; scan based diagnostic schemes; scan chain fault diagnosis; scan path failures; Circuit faults; Circuit testing; Clocks; Dictionaries; Fault diagnosis; Fault location; Logic circuits; Logic design; Logic testing; Process design;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512645
