Title :
Asynchronous multiple scan chains
Author :
Narayanan, Sridhar ; Breuer, Melvin A.
Author_Institution :
Sun Microsyst. Inc., Mountain View, CA, USA
fDate :
30 Apr-3 May 1995
Abstract :
The long test application times needed for scan designs increase the costs of testing. In this paper we introduce the concept of asynchronous multiple scan chains in which groups of scan chains operate independently. This is achieved by using more than one made signal to control the scan flip-flops. Asynchronous multiple chains can provide large reductions in the test application time. We present an efficient test application scheme to exploit the asynchronous operation of the chains. Based on this scheme, we outline techniques to configure the chains so as to minimize the test time. Implementation results show significant savings in test application time and highlight interesting design tradeoffs between the control complexity, I/O pin count and test time
Keywords :
asynchronous circuits; boundary scan testing; design for testability; flip-flops; integrated circuit testing; integrated logic circuits; logic design; logic testing; DFT method; I/O pin count; asynchronous multiple scan chains; control complexity; logic IC; scan designs; scan flip-flops; test application time; Automata; Bandwidth; Circuit testing; Clocks; Costs; Flip-flops; Pins; Sun; Synchronization; Test equipment;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512648