An experimental investigation of current stressing on wafer-level chip-scale packages

We investigated the reliability of a board-level wafer-level chip-scale package (WLCSP) subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 degC. A reasonably good correlation between mean-time-to-failure of the WLCSP test vehicle and the average current density carried by a solder joint was obtained. Moreover, the trace breakage was identified as the mandatory failure mode under these current stressing conditions. In-situ observations were also conducted to further identify this particular failure mode