Scan testing of micropipelines

Author

Petlin, O.A. ; Furber, S.B.

Author_Institution

Dept. of Comput. Sci., Manchester Univ., UK

fYear

1995

fDate

30 Apr-3 May 1995

Firstpage

296

Lastpage

301

Abstract

The micropipeline approach to designing asynchronous VLSI circuits has successfully been used in the AMULET1 microprocessor. A method to design and test micropipelines is presented in this paper. The test strategy is based on the scan test technique. It allows the separate testing of all the data processing blocks by scanning the test patterns in and shifting the responses out of the stage registers. The proposed test approach provides for the detection of all single stuck-at and delay faults in the micropipeline. Tests for the combinational processing logic and state holding elements can be derived using standard test generation techniques

Keywords

VLSI; asynchronous circuits; boundary scan testing; computer testing; delays; design for testability; fault location; integrated circuit design; integrated circuit testing; logic design; logic testing; microprocessor chips; AMULET1 microprocessor; asynchronous VLSI circuit design; combinational processing logic; data processing blocks; delay faults; micropipelines; scan test technique; single stuck-at faults; state holding elements; test generation techniques; test patterns; Asynchronous circuits; Circuit faults; Circuit testing; Clocks; Computer science; Data processing; Delay; Logic testing; Protocols; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1995. Proceedings., 13th IEEE

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7000-2

Type

conf

DOI

10.1109/VTEST.1995.512652

Filename

512652