Title :
Test pattern generation for IDDQ: increasing test quality
Author :
Dalpasso, Marcello ; Favalli, Michele ; Olivo, Piero
Author_Institution :
Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
fDate :
30 Apr-3 May 1995
Abstract :
So far, the test pattern generation for IDDQ testing has been performed without considering the value of the faulty current in comparison with the minimum current that is detectable as a fault: this approach will be shown to be misleading, since it actually gives optimistic coverage evaluation. Then, this work presents an ATPG strategy that targets the highest valves of current during the fault activation, in such a way that either a higher fault coverage can be obtained or a less accurate sensor can be used
Keywords :
CMOS logic circuits; automatic testing; integrated circuit testing; logic testing; ATPG strategy; IDDQ testing; fault coverage; quiescent power supply current monitoring; test pattern generation; Automatic test pattern generation; Bridges; Circuit faults; Circuit testing; Fault detection; Joining processes; Logic gates; Logic testing; Performance evaluation; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512653
