The methods of FPGA software verification

With the FPGA widely applied in embedded system, more and more quality problems related to FPGA began to expose. The verification efficiency of FPGA software needs to be improved urgently. This paper started with the concept of FPGA software, proposing two methods: testbench and assertion analysis to solve the problem of FPGA software verification on the basis of comparing with traditional software. It cited the example of a RISC (Reduced Instruction Set Computer) CPU, described the implementation process of FPGA software verification methods from establishing simulation environment to verifying CPU function of reading and writing memory, and finally validated the effectiveness of the methods.