Test preparation for high coverage of physical defects in CMOS digital ICs

In this paper, a novel methodology for test preparation of digital ICs, aiming at high defect coverage and affordable computational effort, is proposed. A method is presented to heuristically generate a list of pseudo realistic (PSE) faults, at gate level, such that test quality is improved when PSE faults are used in test generation, in addition to normal stuck-at testing. Test quality assessment is performed in the bottom-up phase, using layout data and extracted realistic faults. Experiments are performed using two new tools, tabloid and iceTgen. Simulation examples using ISCAS benchmarks demonstrate that PSE faults can be rewardingly used especially for I_DDQ test generation, leading to very low escape rates