Title :
A scheduling problem in test generation
Author :
Inoue, Tomoo ; Maeda, Hironori ; Fujiwara, Hideo
Author_Institution :
Grad. Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
fDate :
30 Apr-3 May 1995
Abstract :
The order of faults which are targeted for test-pattern generation affects both the processing time for test generation and the number of test-patterns. This order is referred to as a test generation schedule. In this paper, we consider the test generation scheduling problem which minimizes the cost of testing. We analyze the effect of scheduling based on test-pattern generation time and dominating probability. Then, we present experimental results on the ISCAS´85 benchmark circuits
Keywords :
automatic testing; combinational circuits; integrated circuit testing; logic testing; probability; scheduling; ISCAS´85 benchmark circuits; combinational logic circuit testing; dominating probability; processing time; scheduling problem; test generation schedule; test-pattern generation; testing cost; Circuit faults; Circuit testing; Combinational circuits; Costs; Fault detection; Fault diagnosis; Logic testing; Optimal scheduling; Scheduling algorithm; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512659
