Reducing test application time in scan design schemes

Author

Vinnakota, Bapiraju ; Stessman, N.J.

Author_Institution

Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA

fYear

1995

fDate

30 Apr-3 May 1995

Firstpage

367

Lastpage

372

Abstract

We present new methods to reduce test times in sequential circuits using scan. The problem of reducing test application time is shown to be computationally intractable. We discuss heuristic techniques to reduce test times. Fault simulation and correlation between test vectors are used to reduce test times, without affecting fault coverage. Our methods can be used to process a test set after test generation is complete. They lead to a substantial reduction in test times

Keywords

automatic testing; boundary scan testing; correlation methods; fault diagnosis; graph theory; logic testing; sequential circuits; computationally intractable problem; fault coverage; fault simulation; heuristic techniques; scan design schemes; sequential circuits; test application time; test times; test vector correlation; Bipartite graph; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Costs; Design for testability; Integrated circuit testing; Sequential analysis; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1995. Proceedings., 13th IEEE

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7000-2

Type

conf

DOI

10.1109/VTEST.1995.512662

Filename

512662

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2279378