Title :
Electrical characterization of LDP-PBGA package substrate
Author :
Ryu, Carl ; Kwak, Myoung-Bo ; Lee, Hee-seok ; Yim, Sang-il
Author_Institution :
Samsung Electro-Mech., Samsung Electron., Irvine, CA
Abstract :
As semiconductor digital logic and analog I/O bandwidth operates close to 10Gbps ranges, semiconductor package technology requires much tighter attenuation and timing budgets. To overcome electrical performance degradation while maintain cost-performance BOM models, it is required to consider the effect of PBGA package substrate Cu plating bars. In this paper, we analyzed the electrical performance based on the effect of Cu plating bars.
Keywords :
ball grid arrays; copper; integrated circuit modelling; plastic packaging; Cu; Cu plating bars; LDP-PBGA package substrate; analog I/O bandwidth; electrical characterization; plastic ball grid arrays; semiconductor digital logic; semiconductor package technology; timing budgets; Attenuation; Bandwidth; Bars; Bills of materials; Degradation; Logic; Performance analysis; Semiconductor device packaging; Substrates; Timing;
Conference_Titel :
Electronics Packaging Technology Conference, 2006. EPTC '06. 8th
Conference_Location :
Singapore
Print_ISBN :
1-4244-0664-1
Electronic_ISBN :
1-4244-0665-X
DOI :
10.1109/EPTC.2006.342790
