DocumentCode
2279433
Title
Electrical characterization of LDP-PBGA package substrate
Author
Ryu, Carl ; Kwak, Myoung-Bo ; Lee, Hee-seok ; Yim, Sang-il
Author_Institution
Samsung Electro-Mech., Samsung Electron., Irvine, CA
fYear
2006
fDate
6-8 Dec. 2006
Firstpage
651
Lastpage
654
Abstract
As semiconductor digital logic and analog I/O bandwidth operates close to 10Gbps ranges, semiconductor package technology requires much tighter attenuation and timing budgets. To overcome electrical performance degradation while maintain cost-performance BOM models, it is required to consider the effect of PBGA package substrate Cu plating bars. In this paper, we analyzed the electrical performance based on the effect of Cu plating bars.
Keywords
ball grid arrays; copper; integrated circuit modelling; plastic packaging; Cu; Cu plating bars; LDP-PBGA package substrate; analog I/O bandwidth; electrical characterization; plastic ball grid arrays; semiconductor digital logic; semiconductor package technology; timing budgets; Attenuation; Bandwidth; Bars; Bills of materials; Degradation; Logic; Performance analysis; Semiconductor device packaging; Substrates; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2006. EPTC '06. 8th
Conference_Location
Singapore
Print_ISBN
1-4244-0664-1
Electronic_ISBN
1-4244-0665-X
Type
conf
DOI
10.1109/EPTC.2006.342790
Filename
4147319
Link To Document