Synthesis of combinational circuits with special fault-handling capabilities

In this paper we present a new approach to the design of circuits with special properties with regards to internal faults, such as self-checking and fault-tolerant circuits. The approach is based on introducing a minimal amount of redundancy during a multilevel logic optimization process. In this process, we take advantage of the degrees of freedom associated with internal don´t care conditions, in order to minimize the amount of redundancy needed to achieve the desired fault-handling capabilities. Experimental results on several benchmark circuits are presented. They compare very favourably with traditional implementations based on topological augmentation rules