Title :
A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers
Author :
Brown, Steve ; Gutierrez, German ; Nelson, Reed ; VanKrevelen, C.
Author_Institution :
AMCC, San Diego, CA, USA
fDate :
30 Apr-3 May 1995
Abstract :
An integrated circuit for high speed testing which provides precision edge timing and control for three complete channels is described. It consists of nine timing verniers of 40 pS time-step, 80 pS accuracy and 2 nS full range, and all the logic required to configure the drive waveforms and the strobe of the returning signals. The system clock frequency into the IC is 500 MHz
Keywords :
automatic test equipment; clocks; emitter-coupled logic; logic arrays; programmable controllers; timing; 40 ps; 500 MHz; ECL; drive waveforms; gate array; high speed testing; precision edge timing; returning signals; system clock frequency; timing verniers; triple channel ATE controller; Circuit testing; Clocks; Control systems; Electronic equipment testing; High speed integrated circuits; Integrated circuit testing; Logic circuits; Logic testing; System testing; Timing;
Conference_Titel :
VLSI Test Symposium, 1995. Proceedings., 13th IEEE
Conference_Location :
Princeton, NJ
Print_ISBN :
0-8186-7000-2
DOI :
10.1109/VTEST.1995.512676
