Coreless substrate for high performance flip chip packaging

The build-up substrates have been used for flip chip packages in high speed and high performance applications for a long time in a variety of layer stacked substrates such as 3+N+3 or 4+N+4. Because of the needs in high speed applications, the device´s frequency is running fast and the package performance need be improved to achieve such high performance demand. One of solutions is to reduce the core layer thickness from current 800 um down to 400 um or even thinner to 200 um, and it demonstrates the electrical performance has been improved. In this paper, the coreless substrate has been proposed for this study and has been use for flip chip BGA to improve the electrical performance. Coreless flip chip package has several advantages over the thick-core (800 or 400 um) package such as lower parasitic resistance, inductance and capacitance, the interconnect density is also higher for fine pitch and high I/O applications. On the other hand, the coreless package encounters warpage issue during the packaging assembly and reliability test. The properties of coreless material and package structure has been studied and discussed. Finally, the HFCBGA package with two types of dielectric substrates has been built to demonstrate the process capability and packaging robust reliability.