SD-TSOP package thermal design validation and reliability performance evaluation

This paper outlines and demonstrates the advantages of applying both predictive thermal modeling and reliability stressing as design validation strategies in stack die-thin small outline package (SD-TSOP) technology development. JEDEC test standard in both thetas-JA (JESD51-2, junction to still air thermal resistance) and thetas-JB (JESD51-8, junction to board thermal resistance) environments have been introduced as a figure of merit to monitor low density interconnect (LDI) package thermal characteristic post various reliability stressing. In an effort to develop comprehensive understanding of package thermal performance, a commercial computational fluid dynamics (CFD) engineering tool has been employed in board design options, material set, maximum thermal design power (TDP) and die power ratio optimization studies prior to experimental testing. Modeling analysis suggested both board metal layers and die power ratio have significant impact to package thermal performance. Thermal enhancement can be achieved by using higher copper metal layers and lower power ratio on top die. In addition, reliability performance evaluation revealed that SD-TSOP is robust as no significant thermal degradation was observed at the end of the evaluation. Thus, with optimized design and extensive reliability validation, a reliable package thermal design was successfully delivered