Electrical performance analysis of compliant wafer level package (CWLP) with embedded air-gaps

A good solution to meet the need of miniaturization and low cost for micro-electronics packaging is wafer level package technology. But thermal mechanical reliability problem which generated from the coefficient of thermal expansion (CTE) mismatch between the chip and the PCB limit the application of larger size wafer level package. To solve this problem, the prototype of compliant package is proposed in International Technology Roadmap for Semiconductors (ITRS). Firstly, a novel compliant bump structure with embedded air-gaps proposed by Fraunhofer IZM is introduced. Then the process flow of compliant wafer level package (CWLP) with embedded air-gaps is described. The embedded air-gaps are fabricated by MEMS sacrificial layer process, which can adapt certain deformation in the direction of Z-axis. On the plane X-Y, both geometry and size of copper interconnection are optimized and developed, which works as the micro spring to absorb the deformation in the plane X-Y. Subsequently,four structures of micro spring, i.e. straight line sharp, S-sharp, M-sharp and J-sharp, are designed and simulated by the application of HFSS and Q3D softwares under the frequency from 1 to 10GHz. Electrical parameters of the package, i.e. resistance, capacitance and inductance, are computed. The electrical parasites of micro spring are evaluated and compared among four structures mentioned above. Further, the SI, such as return loss, insertion loss, near-end crosstalk and far-end crosstalk are evaluated and compared. The conclusion is that the J-sharp micro spring is better than others in comprehensive performance for CWLP. Finally, effects of geometric parameters on electrical parasitic are studied with Ansoft´s Q3D for J-shape micro spring.