Title :
A novel bandwidth estimation method for distributed on-chip RLCG interconnects
Author :
Kar, Rajib ; Maheshwari, V. ; Choudhary, Aman ; Singh, Abhishek ; Mal, Ashis K. ; Bhattacharjee, A.K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Durgapur, India
Abstract :
Due to the requirement of high data transmission rate, bandwidth has become an important performance parameter for high speed VLSI design. In order to have the maximum data transfer possible through the on-chip data buses, the bandwidth of the interconnect has to be precisely modeled. At very high frequency (of the order of few GHz) both inductance and conductance matrices become equally important for the characterization of the on-chip interconnect. With the increase in the number of metal layers from generation to generation, the coupling has become a crucial phenomenon that could severely affect the performance parameters of the on-chip buses. There are several approaches proposed in the literature which consider only the capacitive coupling between the metal lines. But at the operating frequency, of the order of few GHz, the inductive coupling should also be considered simultaneously for the accurate modeling of the cross talk phenomena. In this paper we have proposed a closed form formula for the bandwidth of on-chip interconnect. For the first time in the literature, we have derived the bandwidth expression for the interconnect using RLCG transmission line model taking inductive coupling into consideration. We have analytically shown the maximum bandwidth achievable from two parallel interconnect lines with a definite amount of inductive coupling present between these two. The results obtained by using our method show that the proposed model could result an error as less as 10% when compared to SPICE simulation.
Keywords :
SPICE; VLSI; bandwidth allocation; data communication; electronic data interchange; multiprocessor interconnection networks; network-on-chip; system buses; transmission lines; RLCG transmission line model; SPICE simulation; VLSI design; bandwidth estimation method; bandwidth expression; capacitive coupling; conductance matrix; data transmission rate; distributed on-chip RLCG Interconnect; inductance matrix; inductive coupling; metal layer; metal line; on-chip data bus; on-chip interconnect bandwidth; parallel interconnect line; Capacitance; Couplings; Crosstalk; Inductance; Integrated circuit interconnections; Integrated circuit modeling; Power transmission lines; Bandwidth Estimation; Crosstalk; Distributed RLCG; Inductive Coupling; On-Chip Interconnect;
Conference_Titel :
Signal and Image Processing (ICSIP), 2010 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4244-8595-6
DOI :
10.1109/ICSIP.2010.5697501