DocumentCode
2280141
Title
An experimental methodology for the estimation of spatially correlated parametric yield in thin film devices
Author
Carlen, E.T. ; Mastrangelo, C.H.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear
1997
fDate
8-10 Sept. 1997
Firstpage
45
Lastpage
48
Abstract
In this paper we present an experimental methodology for parametric yield estimation that accounts for spatial correlations between features of the same device at specific wafer locations. Each device feature is representative of a device parameter that must fit with a specific tolerance box and may be influenced by several steps of the manufacturing process. If the process how is known and each of its steps is characterized in a spatially correlated manner, the feature pointwise probability density functions (PDFs) can be accurately reconstructed from the processing step pointwise PDFs. This method thus permits the estimation of pointwise device yield more accurately than the common multilevel (run, wafer, die) averaging approach. Because spatially correlated phenomena is subject to both random and systematic nonuniformities, the pointwise step (PDFs) are determined by a decomposition process that separates the systematic and random error components. The systematic PDFs are determined from interpolation functions representing the spatial variations across the entire wafer lot, and the random PDFs are approximated using a combination of principle component analysis and factor analysis with a few uncorrelated random variables valid for the entire lot.
Keywords
correlation methods; integrated circuit yield; interpolation; parameter estimation; thin film devices; tolerance analysis; decomposition; device parameter; factor analysis; interpolation function; manufacturing; parametric yield estimation; principle component analysis; probability density function; processing step pointwise PDF; random error; random variable; spatial correlation; systematic error; thin film device; tolerance; wafer lot; Integrated circuit yield; MOSFET circuits; Manufacturing processes; Semiconductor device modeling; Sensor phenomena and characterization; Thin film circuits; Thin film devices; Thin film sensors; Transistors; Yield estimation;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on
Conference_Location
Cambridge, MA, USA
Print_ISBN
0-7803-3775-1
Type
conf
DOI
10.1109/SISPAD.1997.621332
Filename
621332
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