To implement cryptographic model for secure communication on FPGA using 32-bit ALU unit

Cryptography is one of the fundamental components for secure communication of data and authentication. However, cryptographic algorithms impose tremendous processing power demands that can be a bottleneck in high-speed networks. The implementation of a cryptographic algorithm must achieve high processing rate to fully utilize the available network bandwidth. To follow the variety and the rapid changes in algorithms and standards, a cryptographic implementation must also support different algorithms and be upgradeable in field. Otherwise, interoperability among different systems is prohibited and any upgrade results in excessive cost. The ultimate solution for the problem would be an adaptive processor that can provide software-like flexibility with hardware-like performance. Efficient hardware design is essentially a resource allocation problem. The goal is, given the constraints, to find the optimal balance between required silicon area, operation throughput, energy consumption and design time to implement a system. In this paper we have tried to make the 32-bit ALU used for the new algorithm design.