Device and circuit optimization of PHEMT MMIC LNA for low power consumption

Author

Yuk, Jong Seol ; Choi, Byoung Gun ; Park, Chul Soon

Author_Institution

Sch. of Eng., Inf. & Commun. Univ., Taejon, South Korea

Volume

1

fYear

2001

fDate

2001

Firstpage

260

Abstract

This paper presents a low power PHEMT monolithic LNA for C-band applications. A two-stage PHEMT MMIC low noise amplifier with power consumption of 18 mW, low noise figure as low as 1.7 dB with gain 18 dB at 5.8 GHz, has been designed using S- and noise parameters and large signal model. The input return loss and output return loss are better than -17 dB and -20 dB at 5.8 GHz, while drawing only 6 mA from a 3 V supply. This PHEMT MMIC LNA has superior DC power performance while still maintaining low noise figure, compared with other HEMT LNAs at the frequency range

Keywords

HEMT integrated circuits; MMIC amplifiers; S-parameters; circuit optimisation; field effect MMIC; integrated circuit modelling; integrated circuit noise; losses; low-power electronics; 1.7 dB; 18 dB; 18 mW; 3 V; 5.8 GHz; 6 mA; C-band applications; DC power performance; MMIC LNA; PHEMT MMIC; S-parameters; circuit optimization; input return loss; large signal model; low power consumption; noise parameters; output return loss; Circuit noise; Circuit optimization; Energy consumption; Gain; HEMTs; Low-noise amplifiers; MMICs; Noise figure; PHEMTs; Signal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2001. APMC 2001. 2001 Asia-Pacific

Conference_Location

Taipei

Print_ISBN

0-7803-7138-0

Type

conf

DOI

10.1109/APMC.2001.985636

Filename

985636