An ATPG for low power VLSI design using variable length ringcounter & LFSR

A new built-in self-test (BIST) test pattern generator (TPG) for low power testing is presented in this paper. The principle of the proposed approach is to reconfigure the CUT´s partial-acting-inputs into a short ring counter (RC), and keep the CUT´s partial-freezing-inputs unchanged during testing. Experimental results based on ISCAS´85 and ISCAS´89 benchmark circuits show that 17% reductions in the test data storage, 43% reductions in the number of test pattern, 30% reductions in the average power, 19% reductions in the average power and 46% reductions in the total power consumption are attained during testing with a small size decoding logic.