Title :
An ATPG for low power VLSI design using variable length ringcounter & LFSR
Author :
Dhanagopal, R. ; Kavitha, Anbukumar
Author_Institution :
ECE, Jayaram Coll. of Eng. & Tech., Trichy, India
Abstract :
A new built-in self-test (BIST) test pattern generator (TPG) for low power testing is presented in this paper. The principle of the proposed approach is to reconfigure the CUT´s partial-acting-inputs into a short ring counter (RC), and keep the CUT´s partial-freezing-inputs unchanged during testing. Experimental results based on ISCAS´85 and ISCAS´89 benchmark circuits show that 17% reductions in the test data storage, 43% reductions in the number of test pattern, 30% reductions in the average power, 19% reductions in the average power and 46% reductions in the total power consumption are attained during testing with a small size decoding logic.
Keywords :
VLSI; automatic test pattern generation; built-in self test; counting circuits; decoding; design for testability; integrated circuit design; integrated circuit testing; low-power electronics; ATPG; CUT; ISCAS´85 benchmark circuits; ISCAS´89 benchmark circuits; LFSR; built-in self-test; decoding logic; low power VLSI design; low power testing; partial acting input; partial freezing input; power consumption; test data storage; test pattern generator; variable length ring counter; Built-in self-test; Circuit faults; Decoding; Flip-flops; Power demand; Registers;
Conference_Titel :
Signal and Image Processing (ICSIP), 2010 International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4244-8595-6
DOI :
10.1109/ICSIP.2010.5697517
