DocumentCode :
2280271
Title :
Efficient and scalable cache coherence schemes for shared memory hypercube multiprocessors
Author :
Kumar, Akhilesh ; Mannava, Phanindra K. ; Bhuyan, Laxmi N.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear :
1994
fDate :
14-18 Nov 1994
Firstpage :
498
Lastpage :
507
Abstract :
Large scale shared memory multiprocessors use a directory based cache coherence scheme. The basic directory scheme, called full-map, is efficient but has a large memory overhead. Therefore, limited directory schemes have been proposed which limit the number of pointers in the directories. These schemes tradeoff smaller memory overhead for larger memory access latencies. We propose a new limited directory scheme, which achieves lower memory overhead as well as smaller memory access latencies. The scheme uses ring embedding in a hypercube in conjunction with wormhole routing to reduce the invalidation delays. The proposed scheme performs as good as full-map for smaller degree of sharing and performs better than full-map for larger degree of sharing
Keywords :
cache storage; hypercube networks; parallel architectures; reconfigurable architectures; shared memory systems; directory based cache coherence scheme; full-map scheme; invalidation delays; large memory overhead; limited directory schemes; memory access latencies; memory overhead; pointers; ring embedding; scalable cache coherence schemes; shared memory hypercube multiprocessors; wormhole routing; Buildings; Cache memory; Computer science; Delay; Hypercubes; Large-scale systems; Multiprocessor interconnection networks; Protocols; Routing; Scalability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Supercomputing '94., Proceedings
Conference_Location :
Washington, DC
Print_ISBN :
0-8186-6605-6
Type :
conf
DOI :
10.1109/SUPERC.1994.344313
Filename :
344313
Link To Document :
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