• DocumentCode
    2280655
  • Title

    Photoresist process optimization for defects using a rigorous lithography simulator

  • Author

    Milor, L. ; Orth, L. ; Steele, D. ; Khoi Phan ; Xiaolei Li ; Strojwas, A. ; Yung-Tao Lin

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
  • fYear
    1997
  • fDate
    8-10 Sept. 1997
  • Firstpage
    57
  • Lastpage
    60
  • Abstract
    Particulate contamination in photoresist is a major source of yield loss for CMOS processes. Yield loss due to such contamination is controllable by improved filtering. This paper explores the relation between particle size and line spacing for an i-line lithography process using a calibrated defect simulator.
  • Keywords
    filtration; particle size; photoresists; semiconductor process modelling; surface contamination; CMOS IC yield; METROPOLE; calibration; defect simulator; filtering; i-line lithography; line spacing; particle size; particulate contamination; photoresist; process optimization; Absorption; Atmospheric modeling; CMOS process; Computational modeling; Computer simulation; Contamination; Filtering; Lithography; Resists; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on
  • Conference_Location
    Cambridge, MA, USA
  • Print_ISBN
    0-7803-3775-1
  • Type

    conf

  • DOI
    10.1109/SISPAD.1997.621335
  • Filename
    621335
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2280655