Title :
A method for die-scale simulation of CMP planarization
Author_Institution :
TCAD, Intel Corp., Santa Clara, CA, USA
Abstract :
Chemical-Mechanical Polishing (CMP) is well known for its planarization capability. However, it suffers from long-range non-uniformity due to its sensitivity to pattern density. This paper shows that, by using basic building blocks and formulation techniques, CMP simulation can be done on a large dimension, namely the whole die.
Keywords :
polishing; semiconductor process modelling; CMP planarization; chemical-mechanical polishing; die-scale simulation; Chemical processes; Dielectrics; Educational institutions; Image sampling; Numerical models; Planarization; Sampling methods; Semiconductor device modeling; Shape; Slurries;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on
Conference_Location :
Cambridge, MA, USA
Print_ISBN :
0-7803-3775-1
DOI :
10.1109/SISPAD.1997.621337
