DocumentCode
2281293
Title
A 1.5V Low Power CMOS LNA Design
Author
Qi, Hong ; Jie, Zhang
Author_Institution
Anhui Univ., Hefei
fYear
2007
fDate
16-17 Aug. 2007
Firstpage
1379
Lastpage
1382
Abstract
A 1. 5 V 0.18mum CMOS LNA for GPS applications has been designed with fully differential topology. Under such a low supply voltage, the fully differential LNA has been simulated, it provides a series of good results in Noise figure, Linearity and Power consumption. The LNA achieves a Noise figure of 1. 5 dB, voltage gain of 32 dB, Power dissipation of 6 mW, and the input reflection coefficient (Sn) is -23 dB.
Keywords
CMOS digital integrated circuits; integrated circuit design; low noise amplifiers; CMOS LNA design; input reflection coefficient; low supply voltage; noise figure 1.5 dB; power consumption; power dissipation; size 18 mum; voltage 1.5 V; voltage gain; Communications technology; FETs; Impedance matching; Inductors; Low-noise amplifiers; Microwave antennas; Microwave technology; Noise figure; Parasitic capacitance; Wireless communication; 1.5V; IIP3; LNA; low power;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2007 International Symposium on
Conference_Location
Hangzhou
Print_ISBN
978-1-4244-1045-3
Electronic_ISBN
978-1-4244-1045-3
Type
conf
DOI
10.1109/MAPE.2007.4393534
Filename
4393534
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