Millimeter-wave main memory-to-processor data bus

The mainstreaming of chip multiprocessor (CMP) architectures exact a profound impact on valuable resources, for example, L3 cache capacity, off-chip bandwidth and onboard main memory capacity. Even with latency-hiding software strategies, in a memory-starved system, a processor can remain idle for several decades of clock cycles and performance will degrade. Two hardware solutions are being developed for opening the memory bottleneck; (1) Stack bare SRAM die memory, with multiplexer-demultiplexer, using through-silicon vias and place the SRAM stacks around the multi-core processor at the multi-chip carrier level to increase L3 capacity and, in addition, also stack dynamic random access memory (DRAM) dies on board to increase main memory capacity needed for numerically intensive and storage intensive computations. We propose a third option consisting of a wireless data bus, operating in the millimeter wave (mmW) band, which can provide "fetch" and "put" operations between processors and DRAM memory with unprecedented bandwidth. Digitally coded (mmW) are used to transfer data between antenna arrays by means of near field coupling. The main design targets are as follows: (1) single channel throughput 20-40 Gb/s, in a 5-10 GHz frequency bandwidth using 60-90 GHz carrier waves and QPSK and 8PSK symbol coding. Data bandwidth scaling is accomplished by symbol coding, at the expense of greater power dissipation, and is independent of materials. (2) 64 bi-directional channels in the ~4×4 cm² footprint of a packaged processor for an aggregate data rate of 160-320 GB/s. (3) A globally distributed optical clock from an off-board modulated laser provides the correlated, self tracking clock to synchronize memory transfers and provides the local oscillator (LO) port signal to each transmitter (Tx)-receiver (Rx) pair. The global optical clock reduces power consumption and IC component duplication in the Tx/Rx array by replacing frequency synthesizers, voltage con- - trolled oscillators (VCOs) and phase lock loops (PLLs). Only one optical clock drop is required for each Tx/Rx array serving a processor or memory node; (a memory node is the volume of memory addressed by a single controller). (4) Processor cards may contain multiple processors and main memory cards contain large volumes of DRAM and multiple controllers. The two cards are placed back-to-back in adjacent slots. Antenna arrays are mounted on the back of the respective card and face each-other at near-field distances. (5) The integrated circuit (IC) mmW components, such as mixers, frequency multipliers, active filters, low noise amplifiers and power amplifiers are monolithically integrated using the silicon CMOS process at technology nodes 65 nm and 45 nm. A proposed system architecture and antenna design are discussed. Results of near field data transfer experiments using Vivaldi radiators and discrete modular components are summarized.