Parallel and pipelined architecture designs for distributed arithmetic-based recursive digital filters

This paper presents a distributed arithmetic based design scheme for recursive DSP systems requiring high speed computing. The proposed scheme features a bit-serial word-parallel approach and is found more efficient than the conventional bit-parallel word-serial scheme. We apply this scheme to design an ARMA filter and yield an initiation interval as small as the delay of processing only one output bit. We also incorporate the look-ahead transform and the block processing techniques in the proposed DA scheme for further speed improvement. Finally, we propose a signed digit DA scheme to solve the performance degradation problem due to the effect of data word length truncation in fixed point number computing systems