Performance and analysis of CML Logic gates and latches

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. In this work, MOS current mode logic (MCML) is analyzed for application to low power, mixed signal environments. A small MCML cell library is developed and optimized for several different performance requirements. The cells are then applied to the generation of logic gates and latch structures and compared with equivalent CMOS circuits. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh- frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications.