• DocumentCode
    2281916
  • Title

    Energy and performance analysis of mapping parallel multi-threaded tasks for an on-chip multi-processor system

  • Author

    Lai, Bo-Cheng Charles ; Schaumont, Patrick ; Qin, Wei ; Verbauwhede, Ingrid

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
  • fYear
    2005
  • fDate
    2-5 Oct. 2005
  • Firstpage
    102
  • Lastpage
    104
  • Abstract
    Multiprocessor systems offer superior performance and potentially better energy-reduction than single-processor systems. It all depends, however, on how well the application can be mapped onto the architecture. Indeed, a careful tradeoff of energy and performance requires a thorough understanding of the energy consumption pattern of the application across the architecture. We develop a simulation platform, MultiPo-Sim, which returns the cycle-accurate performance and energy consumption of a multiprocessor system, for both hardware components and software primitives. On the hardware level, energy scaling techniques can be modeled and each processing core can operate at different energy modes. MultiPo-Sim achieves 331K cycles per second simulation speed for a four-processor system on a 3GHz, 512MByte Fedora-2 PC. On the software level, data parallelizing and task parallelizing are two common models of multi-thread programming. By using MultiPo-Sim, we show that they show different energy and performance characteristics when mapping onto a multi-processor system.
  • Keywords
    logic design; microprocessor chips; multi-threading; multiprocessing systems; parallel processing; 3 GHz; MultiPo-Sim; data parallelizing; energy consumption pattern; energy scaling techniques; multithread programming; on-chip multiprocessor system; parallel multithreaded tasks; processing core; simulation platform; single-processor systems; task parallelizing; Application software; Computer architecture; Energy consumption; Hardware; Multiprocessing systems; Performance analysis; Power system modeling; Software performance; System-on-a-chip; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
  • Print_ISBN
    0-7695-2451-6
  • Type

    conf

  • DOI
    10.1109/ICCD.2005.47
  • Filename
    1524137