Fast hierarchical process variability analysis and parametric test development for analog/RF circuits

The test development efforts for analog/RF circuits in computer systems today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement set-up requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation that test evaluation requires injecting many parametric deviations into the circuit and analyzing the masking effect of process variations, we develop a hierarchical process variability analysis technique for analog/RF circuits that is specifically geared towards information re-use. We also present a heuristic test selection methodology that aims at providing the same coverage level as the full specification measurements while reducing the test time as well as reliance on hard-to-measure parameters. Experimental results on a differential amplifier circuit confirm the high accuracy of our variance analysis technique and show a 57% reduction in the number of tests after the application of the test selection algorithm.