Drop test simulation of 3D stacked-die packaging with Input-G finite element method

Transient responses of 3D stacked-die package with through silicon via (TSV) structure under board level drop test load following the JEDEC standard are investigated using the Input-G finite element simulation method. In order to reduce the finite element mesh size the stacked-die package under investigation is modeled with details while the others are simplified as blocks with equivalent material properties. The deflection and velocity responses of the stacked-die package located at center of test board are obtained. The stress and strain of the copper via, and micro solder pumps and silicon dies are checked and compared. The simulation results show that the critical position is located at the corner of bottom layer of copper via, copper pad and micro solder bumps. The logarithmic strain evolutions of critical copper pad and micro solder bump are investigated.