DocumentCode :
2282375
Title :
A skewed repeater bus architecture for on-chip energy reduction in microprocessors
Author :
Khellah, Muhammad ; Ghoneima, Maged ; Tschanz, James ; Ye, Yibin ; Kurd, Nasser ; Barkatullah, Javed ; Nimmagadda, Srikanth ; Ismail, Yehea ; De, Vivek
Author_Institution :
Circuits Res., Hillsboro, OR, USA
fYear :
2005
fDate :
2-5 Oct. 2005
Firstpage :
253
Lastpage :
257
Abstract :
This paper proposes a bus architecture called skewed repeater bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing relative delay between neighboring bus lines, SRB reduces both average and worst-case coupling capacitance between those lines. SRB is compared to previously published techniques like delayed data bus (DDB) and delayed clock bus (DCB). Simulation results in 65-nm process show that bus energy reduction of 18% is achieved when SRB is applied to a real microprocessor example, versus 11% and 7% only for DDB and DCB; respectively.
Keywords :
computer architecture; integrated circuit interconnections; microprocessor chips; system buses; 65 nm; bus energy reduction; bus lines; coupling capacitance; delayed clock bus; delayed data bus; microprocessor circuits; on-chip energy reduction; on-chip interconnect energy; skewed repeater bus architecture; Capacitance; Clocks; Coupling circuits; Delay effects; Electronic mail; Frequency; Integrated circuit interconnections; Microprocessors; Pipeline processing; Repeaters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2451-6
Type :
conf
DOI :
10.1109/ICCD.2005.14
Filename :
1524162
Link To Document :
بازگشت