DocumentCode :
2282449
Title :
Architecture of 3D Memory Cell Array on 3D IC
Author :
Lee, Sang-Yun ; Park, Junil
Author_Institution :
BeSang Inc., Beaverton, OR, USA
fYear :
2012
fDate :
20-23 May 2012
Firstpage :
1
Lastpage :
3
Abstract :
High density 3D memory cell array using SGT(Surrounding Gate Transistor) on 3D IC is proposed. SGT with 4F2 cell size shows uniform cell characteristics with a low resistive bit-line path on 3D IC. Parasitic bit-line capacitance of the structure can also be much lower compared to conventional 2D memory cell array or SGT cell array on bulk substrate, which is especially good for memory feature size at or below 10 nm cell node. A combination of 3D memory cell and 3D IC seems to be the ideal memory architecture for the low cost-per- bit of high density memories.
Keywords :
DRAM chips; integrated circuits; transistors; 3D IC; 3D memory cell array architecture; SGT; conventional 2D memory cell array; high density memory; low cost-per-bit; low resistive bit-line path; parasitic bit-line capacitance; surrounding gate transistor; Arrays; Junctions; Logic gates; Microprocessors; Three dimensional displays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Workshop (IMW), 2012 4th IEEE International
Conference_Location :
Milan
Print_ISBN :
978-1-4673-1079-6
Type :
conf
DOI :
10.1109/IMW.2012.6213640
Filename :
6213640
Link To Document :
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