Memory Architecture of 3D Vertical Gate (3DVG) NAND Flash Using Plural Island-Gate SSL Decoding Method and Study of it´s Program Inhibit Characteristics

The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL decoding method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BL´s in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BL´s are grouped together in one unit, and the staircase BL contacts are formed in order to decode various memory layers. Page operation is naturally defined by the selection of each island-gate SSL device. Due to the plural SSL devices, the 3DVG architecture inevitably has more pages when stacked layer number is increased, thus program inhibit stress is much larger than conventional 2D NAND. In this work, the program inhibit performances of 3DVG TFT NAND are discussed. Scaling capability down to 3Xnm node is also demonstrated.