A 64Gb NAND Flash Memory with 800MB/s Synchronous DDR Interface

Author

Huh, Hwang ; Jeon, ChunWoo ; Yang, CheolWoo ; Park, JaeSeok ; Kwon, TaeHeui ; Kang, TaiKyu ; Yang, ChangWon ; Kim, MinSu ; Kim, BumDol ; Park, MyungJin ; Choi, DaeIl ; Park, KangWoo ; Chae, KyeongMin ; Lee, GoHyun ; Oh, SungLae ; Son, ChangMan ; Kim, Yong

Author_Institution

Flash Dev. Div., Hynix Semicond. Inc., Icheon, South Korea

fYear

2012

fDate

20-23 May 2012

Firstpage

1

Lastpage

4

Abstract

We have developed a 64Gb MLC NAND Flash using a sub-20 nm process technology, which realizes 800MB/s data transfer rate with DDR mode. In order to achieve 800MB/s transfer rate, we introduce slim transistors of ~3 nm-thick gate oxide and dual poly gate, in addition to conventional NAND Flash transistors. Furthermore, some new novel circuitry has been implemented, such as Split Power Page Buffer, Local Sense-Amplifier (LSA) Data In/Out Architecture, Regulated Widlar Reference Generator and Low VCC Row Decoder.

Keywords

NAND circuits; buffer circuits; flash memories; transistors; DDR mode; LSA; MLC NAND flash; NAND flash memory; NAND flash transistors; bit rate 800 Mbit/s; data in architecture; data out architecture; data transfer rate; dual poly gate; gate oxide; local sense-amplifier; low VCC row decoder; regulated widlar reference generator; slim transistors; split power page buffer; synchronous DDR interface; word length 64 bit; Computer architecture; Decoding; Flash memory; Logic gates; Microprocessors; Sensors; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Workshop (IMW), 2012 4th IEEE International

Conference_Location

Milan

Print_ISBN

978-1-4673-1079-6

Type

conf

DOI

10.1109/IMW.2012.6213644

Filename

6213644