Title :
Restrictive compression techniques to increase level 1 cache capacity
Author :
Pujara, Prateek ; Aggarwal, Aneesh
Author_Institution :
Dept. of Electr. & Comput. Eng., Binghamton Univ., NY, USA
Abstract :
Increasing cache latencies limit L1 cache sizes. In this paper we investigate restrictive compression techniques for level 1 data cache, to avoid an increase in the cache access latency. The basic technique - all words narrow (AWN) - compresses a cache block only if all the words in the cache block are of narrow size. We extend the AWN technique to store a few upper half-words (AHS) in a cache block to accommodate a small number of normal-sized words in the cache block. Further, we make the AHS technique adaptive, where the additional half-words space is adaptively allocated to the various cache blocks. We also propose techniques to reduce the increase in the tag space that is inevitable with compression techniques. Overall, the techniques in this paper increase the average L1 data cache capacity (in terms of the average number of valid cache blocks per cycle) by about 50%, compared to the conventional cache, with no or minimal impact on the cache access time. In addition, the techniques have the potential of reducing the average L1 data cache miss rate by about 23%.
Keywords :
cache storage; data compression; pipeline processing; resource allocation; L1 cache size; adaptive AHS technique; additional half-words space; all words narrow technique; cache access latency; cache access time; cache block compression; data cache miss rate; level 1 cache capacity; restrictive compression; Automated highways; Decoding; Delay; Energy consumption; Open area test sites; Read-write memory; Wire;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN :
0-7695-2451-6
DOI :
10.1109/ICCD.2005.94